The 64K memory address limit can be extended using a technique called bank or page switching. The operating system can select which page(s) are addressed at any given time. On the MTX computer, the page port, (Output Port 0), is used to control memory addressing using the 74LS373 octal latch in position 5A on the system board.

Page Port Structure Bit D7 D6 D5 D4 D3 D2 D1 D0 Function RELCPMH R2 R1 R0 P3 P2 P1 P0   Mode ROM RAM   Bits D0 to D3 (P0 to P3) define the RAM page address Bits D4 to D6 (R0 to R2) define the ROM page address Bit D7 (RELCPMH) defines a ROM based system (D7 = 0) , or   defines a RAM based system (D7 = 1) The paged memory map structure of the MTX computers was designed to operate in two modes, ROM based (RELCPMH = 0) and RAM based  (RELCPMH = 1).   [Andy has advised that the acronym for bit 7 is Rom Enable if Low, CP / M if High.]

 

ROM Based Memory Map - RELCPMH = 0

When ROMs are enabled, they are mapped from 0 to 3FFFh. The 8K (2000h bytes) monitor ROM is always available in area 0 to 1FFFh and the paged ROMs of 8K (2000h bytes) each are mapped from 2000h to 3FFFh as eight pages 0 to 7 set by R2, R1, R0 in the page port, write only register.

• Up to 512K of RAM is mapped on 16 pages (0 to F) set up by P3, P2 ,P1 and P0 in the page port write only register.

• The area C000h to FFFFh is a 16K (4000h bytes) block common to all RAM pages.

• The 32K (8000h bytes) block from 4000h to BFFFh is mapped as 16 pages.

• The 32K bytes of RAM for an MTX500 is mapped from 8000h to FFFFh (page 0).

• The 64K bytes of RAM for an MTX512 is mapped from 4000h to FFFFh (page 0).

  • The additional 16K is mapped from 8000h to C000h on page 1.

RAM Based Memory Map - RELCPMH = 1

All ROMs are switched out in this mode and up to 16 pages of 48K (C000h bytes) are mapped from 0 to BFFFh. These pages are set by P3, P2, P1 and P0 in the page port write only register. In the area C000h to FFFFh is a 16K block (4000h bytes) of RAM common to all pages.